The present invention relates to a frequency multiplication circuit for generating an output clock signal containing a frequency into which an outside clock signal is multiplied by a predetermined numerical value.
With an advancement of a semiconductor technology over the recent years, it has been a tendency that an operating frequency of an integrated circuit of a microprocessor, a microcontroller and so on. Accordingly, an oscillator for supplying the integrated circuit with the operating frequency is required to generate a clock signal having a higher frequency. When making an attempt to increase the frequency of the clock signal generated by the oscillator, however, there arise such drawbacks that the electric power consumed by the oscillator increases, and that radiation noises produced within the oscillator augment.
A method involving the use of a frequency multiplication circuit has hitherto been known as a method of obviating those drawbacks. According to this method, the clock signal generated by the oscillator having a comparatively low frequency is used as a system clock in an electronic circuit and an electronic appliance that are mounted with a microprocessor and a microcontroller, and a clock signal obtained by multiplying this system clock in a frequency multiplication circuit is employed as an operating clock of the microprocessor and the microcontroller.
FIG. 11 is a block diagram showing one example of a construction of the prior art frequency multiplication circuit.
Referring to FIG. 11, a voltage control oscillation circuit 1101 output s clock signal of a frequency corresponding to a signal voltage inputted from a loop filter 1106. Then, this clock signal is outputted to outside as an output clock signal CLK2 via a clock driver 1102, and at the same time inputted to an N-bit up-counter 1103. Upon this process, the up-counter 1103 counts the number of clocks of the signals outputted from the voltage control oscillation circuit 1101. Then, when this count value reaches a predetermined value, a signal level of a most-significant-bit signal SN-1 of the up-counter 1103 changes from low to high.
A phase detection circuit 1104 inputs the most-significant-bit signal SN-1 from the up-counter 1103 and also an external clock signal CLK1 from outside, and compares phases of these two signals SN-1 and CLK1. Then, a signal Sp indicating a result of detecting a phase difference between the two signals SN-1 and CLK1, is outputted.
A charge pump circuit 1105 inputs this signal Sp and converts it into a voltage signal VC for controlling the above voltage control oscillation circuit 1101. Subsequently, a waveform of this voltage signal VC is shaped by the loop filter 1106 and thereafter inputted to the voltage control oscillation circuit 1101.
According to the thus constructed frequency multiplication circuit, if the phase of the output signal SN-1 of the up-counter 1103 is faster than the phase of the external clock signal CLK1, the frequency of the clock signal generated by the voltage control oscillation circuit 1101 decreases. Whereas if the phase of the output signal SN-1 of the up-counter 1103 is slower than the phase of the external clock signal CLK1, the frequency of the clock signal generated by the voltage control oscillation circuit 1101 increases. Then, the frequency of the clock signal generated by the voltage control oscillation circuit 1101 can be thereby made coincident precisely with an N-fold value of the frequency of the external clock signal CLK1.
The prior art frequency multiplication circuit as illustrated in FIG. 11 has, however, a drawback of increasing both a size and a price of the circuit because of a large number of elements.
Further, it is required that the voltage control oscillation circuit 1101, the charge pump circuit 1105 and the loop filter 1106 be constructed of analog circuits, and hence it is difficult to make a power supply in use compatible with other circuits (i.e., digital circuits). This is also one of the factors to bring about the increases both in the size and in the price of the circuit. Namely, the power supply for operating those analog circuits 1101, 1105, 1106 must be provided separately from a power supply for operating the digital circuits, and therefore totally two units of power supplies are to be required as the case may be.
Moreover, the frequency multiplication circuit shown in FIG. 11 is limited in terms of an external clock signal frequency range enough to match with the voltage control oscillation circuit 1101, and therefore possesses such a drawback that the frequency range of the usable external clock signal is small.
For this reason, there has hitherto been desired a frequency multiplication circuit that is small in circuitry size, constructible of only a digital circuit, and has a wider frequency range of the usable external clock signal.